A clock signal generation circuit which generates a plurality of clock signals having mutually differing phases is used in an orthogonal transformation circuit of a communication instrument, asynchronous dynamic random access memory (SDRAM), and the like. Such a clock signal generation circuit includes, for example, a PLL circuit or a DLL circuit. The generated plurality of clocks are, for example, four clock phases having phase differences of 0°, 90°, 180°, and 270° with a phase of a reference clock, in this case, the four clocks have a phase difference of 90° each in order.
Japanese Laid-open Patent Publication No. 2007-102483 and Japanese Laid-open Patent Publication No. 2006-211208 both disclose a clock generation circuit which generates four-phase clocks. In the clock generation circuits disclosed in these patent documents, a voltage-controlled oscillation circuit (VCO) included in the clock generation circuit generates the four-phase clocks. Also, the voltage-controlled oscillation circuit corrects a variation in phase difference between the four clocks arising due to a characteristic error of the clock generation circuit, or the like, and generates four-phase clocks which have an ideal phase difference.
A circuit is known that generates clocks of an even number of phases, for example, four phases. This known circuit generates a high speed clock having a frequency four times that of clocks to be generated, and divides the frequency of the high speed clock. In a circuit which generates four-phase clocks of 300 MHz to 3 GHz, called a UHF band, it is necessary to generate a high speed clock of a frequency four times that of the UHF band. For this reason, when the clock generation circuit is realized with an LC resonance type of VCO, which has a high power consumption, the circuit becomes one with a large chip area, and expensive.
Unlike the circuit which divides the frequency of a high speed clock with a frequency four times that of the clocks to be generated, a ring oscillator type of VCO, which generates four-phase clocks, may not generate a high speed clock. However, a variation in phase differences between the clocks may arise due to a characteristic error of the circuit, or the like. Consequently, with such a VCO, a shipping test may be performed to determine whether or not the phase differences between the clocks are within an allowable range.
As it is difficult to measure the phase differences of four-phase clocks of, for example, 300 MHz to 3 GHz with a testing device, there is desired a clock generation circuit wherein determining whether or not the variation in the phase differences between the clocks is within an allowable range may performed using a simple method.